When a new computer system is designed, it must be tested to determine its operating parameters and tolerances. This includes the time intervals it takes system elements to perform assigned tasks and deliver requested data or information to the other system elements or external devices.
One of the items that it is often necessary to empirically measure is the maximum time interval that is required for system elements to respond when addressed. Specifically, in computer systems, the time required for a slave device to respond when addressed by a bus master may vary. It is usually necessary to know the system's "worst case" operating conditions so that other system functions may be determined.
There are three techniques for measuring or estimating the maximum response time for system elements. The first technique involves the use of a logic analyzer. For this purpose, the logic analyzer may be attached to a bus to simply measure the time interval system elements take to respond to a request. In performing this function, the logic analyzer measures the time period from when a system element is granted a bus to when a response is provided and the bus is released. To do this, the logic analyzer monitors the computer system under test and triggers whenever the time interval being measured exceeds a predetermined threshold value. The logic analyzer then determines the actual length of the response time interval, resets the threshold to the new higher measured value, resets the trigger, and monitors the bus for the occurrence of a longer response time interval by a system element.
When a logic analyzer is used in this way, there are several drawbacks. Two of the major ones will now be discussed. First, a logic analyzer is a bulky and expensive piece of laboratory equipment. Accordingly, its use for the purpose of measuring the longest time interval for system elements to respond to requests, for example, from a bus master, is restricted primarily to the laboratory environment. It would be very difficult to move a logic analyzer and use it in the field as is required in many cases when a new computer system is being tested.
Second, a logic analyzer is a device that samples data, for example on a bus, for a certain time period at predetermined intervals. It is not usually run for the entire time a new computer system is tested. When a logic analyzer monitors a bus for the purpose of determining the longest response time for system elements, the actual determination of the longest response time interval usually requires many seconds, and even minutes, because the logic analyzer must first capture the data, and then, off-line, analyze the data to determine if a particular threshold value is surpassed, reset the threshold value if it is surpassed, and reset itself to capture more data because of the storage limitations of logic analyzers. Given that response time intervals can be in the order of nanoseconds, there can be millions of response time intervals occurring during the time the logic analyzer is performing the above-discussed functions off-line and one of these time intervals may be the longest response time interval --which is missed--thereby inaccurate results from the logic analyzer will obtain. To attempt to overcome this problem, logic analyzers monitor a bus for an extended period of time to reduce the probability of missing the longest response time interval. This is a very inefficient use of logic analyzers and is an inefficient method to determine the longest response time interval.
The second technique is directed to the use of a timeout circuit that has a fixed threshold value. The timeout circuit may be easily incorporated into a computer system. This circuit operates such that when the threshold value is exceeded, the circuit causes an indication of same by activating a display. This circuit may be implemented in almost any type of computer system and is not restricted to the laboratory environment like a logic analyzer. The circuit also does not miss any time intervals since it performs real-time monitoring of response time intervals and real-time indications of when a response time interval exceeds the threshold value.
The problem with a timeout circuit is that it does not actually measure the response time interval but merely indicates when a response time interval is longer than the threshold value. At best, this technique only verifies whether a particular response time interval is longer or shorter than the threshold value, nothing more.
The third technique overcomes some of the problems that occur in the first two techniques. This technique also is configured as a circuit that may be implemented as part of a computer system. This circuit, unlike the time-out circuit, actually measures the length of each response time interval and compares it with a value that is loaded in the circuit's register. The value in the register is the longest response time value for a system element that has been measured up to the current time. When a longer response time interval is measured, the circuit loads the new value into the register.
A circuit according to the third technique is shown generally at 100 in FIG. 1. The circuit includes control logic 102 which controls operation of the circuit. The first input to control logic 102 is the INTERVAL signal on line 104. This is asserted when a response time interval begins and de-asserted when a response time interval ends. The second input to control logic 102 is the output of comparator 112 on line 118. This signal will be discussed in detail subsequently.
Control logic 102 has two outputs. The first output on line 106 is to counter 108. This output causes the counter to count upward according to the clock rate once the INTERVAL signal is asserted. The second output from control logic 102 on line 107 is input to register 113. The signal on line 107 is the LOAD VALUE signal which causes register 113 to latch the value that is on line 110.
Counter 108 has two inputs. The first input on line 106, as stated, is from control logic 102 and causes the counter to count upward. The other input on line 109 is the RESET signal that resets the counter after the INTERVAL signal is de-asserted.
The output of counter 108 on line 110 is input to comparator 112 and register 113. The second input to comparator 112 is the output of register 113 on line 114. The output of register 113 on line 114 is the value that is latched in register 113 which is the current longest response time interval that has been measured. The output of register 113 also is input to display 116 which displays the current longest response time interval that has been measured.
The output of comparator 112 on line 118 is asserted when the output of counter 108 on line 110 exceeds the value that is latched in register 113 (and input to the comparator on line 114). When the output of comparator 112 on line 118 is asserted, it causes the control logic to assert the LOAD VALUE signal on line 107, once the INTERVAL signal is de-asserted, to load the new longest response time interval value in register 113.
Once a particular response time interval is over and the old value loaded in register 113 has been exceeded, the INTERVAL signal on line 104 is de-asserted, the new value is loaded into register 113, and the counter is reset by asserting the RESET signal on line 109. The circuit operates in the above-described manner during the test period to determine the longest response time interval for the system elements.
The present invention provides an improved method to measure response time intervals as will be described in the remainder of the specification and with reference to the attached drawings.